This invention relates generally to application-specific integrated circuits (ASICs) and programmable logic device (PLD), and more particularly to systems and methods for automated control/monitoring code generation for ASICs and PLDs.
Continuing advances in semiconductor technology have made the integration of increasingly complex functionality possible on a single chip. Single chips are now capable of performing the functions of entire multi-chip systems of years past. For example, today's system-on-a-chip (SoC) may include millions of gates and perform numerous digital, analog, and mixed-signal functions supporting, for example, an embedded system—all on a single substrate.
Typical SoC designs include a controller core (e.g., a microcontroller, microprocessor, or digital signal processor (DSP) core), memory blocks (e.g., ROM, RAM, EEPROM, flash, and hybrid types of memory), peripherals (e.g., counters, timers, and power-on reset generators), and external interfaces all connected by either a proprietary or industry-standard bus. Direct memory access (DMA) controllers may route data directly between the external interfaces and the memory blocks bypassing the controller core. In addition to the hardware described above, an SoC also typically includes associated software that controls the controller core, peripherals, and interfaces. While providing new opportunities, increasingly complex SoCs pose new challenges to the system designer. In particular, conventional design and verification methodologies are often unacceptably time-consuming for large SoC's.
Integrated circuits containing programmable logic, such as field-programmable gate array (FPGAs), are designed to be configured or programmed by a consumer or designer after manufacture of the integrated circuit. PLDs can generally be used to implement any logical function that an ASIC can perform, but the PLD is typically more attractive for some applications due to the ability to update or change the functionality of the PLD after shipping, partial reconfiguration of a portion of the design, and the low non-recurring engineering costs relative to an ASIC design. Today's PLDs, like their ASIC counterparts, may include millions of gates and perform numerous logical functions.
Designers of both PLDs and ASICs may formally describe the digital logic using a hardware description language (HDL), such as VHDL or Verilog. The HDL may be used to describe the circuit's operation, its design and organization, and may also be used to verify its operation by means of simulation. For example, in order to verify that a given HDL design performs correctly, it is common to build a behavioral (e.g., functional) model or logic simulation of the circuit in a software language such as C or C++. The results of the software model or simulation are then compared against those of the HDL model. The software and HDL model must be kept consistent with each other throughout design changes, and changes to one model must be reflected in the other. Making such changes is typically time-consuming and a largely manual process that increases the chance of introducing inconsistencies between the two models. The complexity of making such changes increases if large teams of engineers are involved in the design process.
In addition, modern SoC, ASIC and PLD designs often have hundreds or even thousands of on-chip registers that are used to configure the device for different modes of operation. These memory elements play a critical role in the proper functioning of the device and must be thoroughly verified prior to tape-out. Register verification is becoming an increasingly complex and challenging task. Register specifications, including, for example, address ranges, reset values, and access modes, may change throughout the design process. These changes must be propagated throughout the verification environment and the various test bench components. Updating the test bench every time a single register is added, a field is changed, or a memory is modified becomes a very time-consuming task. In addition, manual approaches to register verification can easily miss errors or bugs, especially as the number of registers to be verified increases.
Moreover, documentation is often not created for the control, monitor, or configuration portions of an ASIC or PLD until very late in the system development cycle. Multiple designers may also develop similar logic differently so that there is typically no standardized way to implement common functions and little consistency between designs. In addition, changes to the logical design of the system may occur frequently, be very time-consuming to implement, and are often not effectively incorporated into the documentation.
Documentation, if any exists, may also become poorly matched with the HDL code and simulation/control software over time. This may result in hidden fields and hidden side effects that are not documented or documented very poorly. These hidden fields and hidden side effects often make use and debugging of the system very frustrating and time consuming.